In modern data processing systems, it is becoming more and more important to make most efficient use of the available memory bandwidth. For example, in System on Chips (SoCs), there are various master devices such as graphics processing units (GPUs) and display controllers that can issue transactions involving the writing or reading of significant quantities of data. It is known to issue transactions as burst transactions, consisting of a plurality of beats, with a certain amount of data being written to memory, or read from memory, during each beat. Such burst transactions can make very efficient use of memory bandwidth. However, there is a limitation that any particular transaction has to be processed by a particular slave device. In modern systems, multiple memory devices may be provided within, or connected to, the SoC, and data may be interleaved amongst those various devices, and this can limit the amount of data that can be addressed by any particular transaction.
In addition, modern SoCs typically include multiple master devices, each of which may contain one or more levels of cache. This gives rise to cache coherency issues, and typically the interconnect circuitry interconnecting the various master devices and slave devices includes cache coherency circuitry (for example snoop circuitry) to ensure that the cache contents are kept coherent, and that accordingly each master device will access up-to-date data. At the time a transaction is issued, then assuming that transaction specifies an address which is cacheable, it will not be known at the time the transaction is issued whether the data at that address is cached or not. It will hence not be known whether the data will be accessed in the cache, or in memory. Typically this limits the amount of data addressed by any particular transaction to not exceed the size of a cache line, hence ensuring that any particular transaction can be serviced by an access to the cache if that data resides in the cache. For burst transactions, this hence limits the overall size of the burst. Whilst such an approach ensures that cache coherency can be maintained in a simple and effective manner, it reduces the efficient use of the available memory bandwidth due to the need to handle multiple smaller burst transactions. The use of such smaller bursts also increases the power consumption within the interconnect circuitry, and can reduce the re-ordering capabilities of memory controllers due to effectively reducing visibility of future transactions in their re-ordering queues, therefore reducing memory efficiency.
US 2010/0042759 provides a mechanism for allowing two or more memory devices to be treated as a single aggregate target. As a result, a master device can issue a transaction to that single aggregate target, allowing a larger burst transaction to be specified. The single transaction is then split up for sending to the various slave devices. However, the results then need to be recombined so that they can be returned to the master from the single aggregate target to which the original transaction was directed. This gives rise to complexity in coordinating the results.
The above described problems associated with the efficient handling of transactions between master and slave devices in a SoC can also occur for other types of transactions issued within the SoC. For example, a master device may issue transactions to interconnect circuitry that identify cache maintenance operations to be performed in respect of a plurality of cache storage devices within the SoC. Since it may not be known which particular cache storage device or cache storage devices need to implement the cache maintenance operation at the time the associated transaction is issued to the interconnect circuitry, it is typical to limit each transaction to address a single cache line of data. Hence, it is typically necessary to issue multiple separate transactions in order to perform cache maintenance operations in respect of multiple cache lines. This tends to increase the power consumption within the interconnect.
It would accordingly be desirable to provide an improved mechanism for handling transactions within a data processing system.